CD4085B系列介绍资料

h1_key

您当前的位置：首页 > 逻辑和电压转换 > 逻辑门 > 组合门 > CD4085B

CD4085B

正在供货

CMOS 双路 2 宽度双输入与或非门

立即搜索现货

产品详情|
产品购买|

产品详情

说明
特性
参数
封装 | 引脚 | 尺寸

CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.

The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Medium-speed operation - t_PHL = 90 ns; t_PLH = 125 ns (typ.) at 10 V
Individual inhibit controls
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range):
- 1 V at V_DD = 5 V
- 2 V at V_DD = 10 V
- 2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Technology family	CD4000
Supply voltage (min) (V)	3
Supply voltage (max) (V)	18
Number of channels	2
Inputs per channel	2
IOL (max) (mA)	6.8
IOH (max) (mA)	-6.8
Input type	Standard CMOS
Output type	Push-Pull
Features	Standard speed (tpd > 50ns)
Data rate (max) (Mbps)	8
Rating	Catalog
Operating temperature range (°C)	-55 to 125

PDIP (N)	14	181.42 mm² 19.3 x 9.4
SOIC (D)	14	51.9 mm² 8.65 x 6
TSSOP (PW)	14	32 mm² 5 x 6.4

产品购买

商品型号
封装
工作温度
包装
价格
现货库存
操作

海量现货，种类齐全
报价讯捷，闪电出货
原厂渠道，正品保证
批量采购，支持议价
专属客服，一对一服务

10s

温馨提示：

订单商品问题请移至我的售后服务提交售后申请，其他需投诉问题可移至我的投诉提交，我们将在第一时间给您答复

* 我的问题/建议：
* 联系电话：
上传图片（选填）：	请您提交2M以内的jpg,gif,png格式文件
投诉订单号（选填）：

h1_key

CD4085B

CMOS 双路 2 宽度双输入与或非门

4000-306-326