These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
| Technology family | LVT |
| Supply voltage (min) (V) | 2.7 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 4 |
| IOL (max) (mA) | 64 |
| Supply current (max) (µA) | 7000 |
| IOH (max) (mA) | -32 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Features | Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SOP (NS) | 14 | 79.56 mm² 10.2 x 7.8 |
| SSOP (DB) | 14 | 48.36 mm² 6.2 x 7.8 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
| TVSOP (DGV) | 14 | 23.04 mm² 3.6 x 6.4 |
| VQFN (RGY) | 14 | 12.25 mm² 3.5 x 3.5 |