h1_key

TI(德州仪器) SN74HC191
德州仪器 (TI) 全系列产品在线购买
  • TI(德州仪器) SN74HC191
  • TI(德州仪器) SN74HC191
  • TI(德州仪器) SN74HC191
  • TI(德州仪器) SN74HC191
  • TI(德州仪器) SN74HC191
  • TI(德州仪器) SN74HC191
立即查看
您当前的位置: 首页 > 逻辑和电压转换 > 触发器、锁存器和寄存器 > 计数器 > SN74HC191
SN74HC191

SN74HC191

正在供货

4 位同步加/减二进制计数器

产品详情
  • 说明
  • 特性
  • 参数
  • 封装 | 引脚 | 尺寸

The ’HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.

These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times.

These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.

Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation.

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Single Down/Up Count-Control Line
  • Look-Ahead Circuitry Enhances Speed of Cascaded Counters
  • Fully Synchronous in Count Modes
  • Asynchronously Presettable With Load Control

FunctionCounter
Bits (#)4
Technology familyHC
Supply voltage (min) (V)2
Supply voltage (max) (V)6
Input typeStandard CMOS
Output typePush-Pull
FeaturesBalanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
Operating temperature range (°C)-40 to 85
RatingCatalog
PDIP (N)16181.42 mm² 19.3 x 9.4
SOIC (D)1659.4 mm² 9.9 x 6
SOP (NS)1679.56 mm² 10.2 x 7.8
产品购买
  • 商品型号
  • 封装
  • 工作温度
  • 包装
  • 价格
  • 现货库存
  • 操作
10s
温馨提示:
订单商品问题请移至我的售后服务提交售后申请,其他需投诉问题可移至我的投诉提交,我们将在第一时间给您答复
返回顶部