CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates.
The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Data sheet acquired from Harris Semiconductor
| Technology family | CD4000 |
| Supply voltage (min) (V) | 3 |
| Supply voltage (max) (V) | 18 |
| Number of channels | 4 |
| Inputs per channel | 2 |
| IOL (max) (mA) | 6.8 |
| IOH (max) (mA) | -6.8 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | High speed (tpd 10- 50ns) |
| Data rate (max) (Mbps) | 8 |
| Rating | Catalog |
| Operating temperature range (°C) | -55 to 125 |
| PDIP (N) | 14 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SOP (NS) | 14 | 79.56 mm² 10.2 x 7.8 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
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