The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.
The SN74F112 is characterized for operation from 0°C to 70°C.
| Number of channels | 2 |
| Technology family | F |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | TTL |
| Output type | Push-Pull |
| Clock frequency (MHz) | 100 |
| Supply current (max) (µA) | 19000 |
| IOL (max) (mA) | 20 |
| IOH (max) (mA) | -1 |
| Features | Clear, Negative edge triggered, Preset, Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | 0 to 70 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| SOP (NS) | 16 | 79.56 mm² 10.2 x 7.8 |
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