CD74AC175系列介绍资料

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CD74AC175

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具有复位功能的四通道 D 类触发器

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This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Buffered Inputs
Contains Four Flip-Flops With Double-Rail Outputs
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators

Number of channels	4
Technology family	AC
Supply voltage (min) (V)	1.5
Supply voltage (max) (V)	5.5
Input type	Standard CMOS
Output type	Push-Pull
Clock frequency (max) (MHz)	100
IOL (max) (mA)	24
IOH (max) (mA)	-24
Supply current (max) (µA)	160
Features	Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
Operating temperature range (°C)	-55 to 125
Rating	Catalog

SOIC (D)

59.4 mm² 9.9 x 6

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CD74AC175

具有复位功能的四通道 D 类触发器

4000-306-326