The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-
termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the CY74FCT373T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Number of channels | 8 |
| Technology family | FCT |
| Supply voltage (min) (V) | 4.75 |
| Supply voltage (max) (V) | 5.25 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Clock frequency (max) (MHz) | 70 |
| IOL (max) (mA) | 12 |
| IOH (max) (mA) | -12 |
| Supply current (max) (µA) | 200 |
| Features | Balanced outputs, Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
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