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TI(德州仪器) SN74ABT126
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  • TI(德州仪器) SN74ABT126
  • TI(德州仪器) SN74ABT126
  • TI(德州仪器) SN74ABT126
  • TI(德州仪器) SN74ABT126
  • TI(德州仪器) SN74ABT126
  • TI(德州仪器) SN74ABT126
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SN74ABT126

SN74ABT126

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具有 TTL 兼容型 CMOS 输入和三态输出的 4 通道、4.5V 至 5.5V 缓冲器

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The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Technology familyABT
Supply voltage (min) (V)4.5
Supply voltage (max) (V)5.5
Number of channels4
IOL (max) (mA)64
Supply current (max) (µA)30000
IOH (max) (mA)-32
Input typeTTL-Compatible CMOS
Output type3-State
FeaturesOver-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)
RatingCatalog
Operating temperature range (°C)-40 to 85
PDIP (N)14181.42 mm² 19.3 x 9.4
SOIC (D)1451.9 mm² 8.65 x 6
SOP (NS)1479.56 mm² 10.2 x 7.8
SSOP (DB)1448.36 mm² 6.2 x 7.8
TSSOP (PW)1432 mm² 5 x 6.4
VQFN (RGY)1412.25 mm² 3.5 x 3.5
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