This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Technology family | LVT |
| Supply voltage (min) (V) | 2.7 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 4 |
| IOL (max) (mA) | 64 |
| Supply current (max) (µA) | 7000 |
| IOH (max) (mA) | -32 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Features | Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SOP (NS) | 14 | 79.56 mm² 10.2 x 7.8 |
| SSOP (DB) | 14 | 48.36 mm² 6.2 x 7.8 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
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