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TI(德州仪器) SN74LVTH241
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  • TI(德州仪器) SN74LVTH241
  • TI(德州仪器) SN74LVTH241
  • TI(德州仪器) SN74LVTH241
  • TI(德州仪器) SN74LVTH241
  • TI(德州仪器) SN74LVTH241
  • TI(德州仪器) SN74LVTH241
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SN74LVTH241

SN74LVTH241

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具有总线保持、TTL 兼容型 CMOS 输入和三态输出的 8 通道、2.7V 至 3.6V 缓冲器

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These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH241 devices are organized as two 4-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low or 2OE is high, the devices pass noninverted data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Technology familyLVT
Supply voltage (min) (V)2.7
Supply voltage (max) (V)3.6
Number of channels8
IOL (max) (mA)64
Supply current (max) (µA)5000
IOH (max) (mA)-32
Input typeTTL-Compatible CMOS
Output type3-State
FeaturesBus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)
RatingCatalog
Operating temperature range (°C)-40 to 85
SOIC (DW)20131.84 mm² 12.8 x 10.3
SSOP (DB)2056.16 mm² 7.2 x 7.8
TSSOP (PW)2041.6 mm² 6.5 x 6.4
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