CD74HCT109系列介绍资料

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CD74HCT109

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具有设置和复位功能的高速 CMOS 逻辑双通道上升沿 J-K 触发器

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The ’HC109 and ’HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

Asynchronous Set and Reset
Schmitt Trigger Clock Inputs
Typical f_MAX = 54MHz at V_CC = 5V, C_L = 15pF, A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Number of channels	2
Technology family	HCT
Supply voltage (min) (V)	4.5
Supply voltage (max) (V)	5.5
Input type	TTL
Output type	Push-Pull
Clock frequency (MHz)	24
Supply current (max) (µA)	40
IOL (max) (mA)	6
IOH (max) (mA)	-6
Features	Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)	16	181.42 mm² 19.3 x 9.4
SOIC (D)	16	59.4 mm² 9.9 x 6

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CD74HCT109

具有设置和复位功能的高速 CMOS 逻辑双通道上升沿 J-K 触发器

4000-306-326