The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected.
Data sheet acquired from Harris Semiconductor
| Number of channels | 16 |
| Technology family | HCT |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | TTL-Compatible CMOS |
| Output type | CMOS |
| Clock frequency (max) (MHz) | 25 |
| IOL (max) (mA) | 4 |
| IOH (max) (mA) | -4 |
| Supply current (max) (µA) | 80 |
| Features | Partial power down (Ioff), Standard speed (tpd > 50ns), Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
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