CD74HC354系列介绍资料

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CD74HC354

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具有三态输出的高速 CMOS 逻辑 8 输入多路复用器/寄存器

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The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE.

In the HC/HCT354 the data enable input, E, controls transparent latches that pass data to the outputs when E is high and latches in new data when E is low.

In both types the three-state outputs are controlled by three output-enable inputs OE1, OE2, and OE3.

HC/HCT354
- Transparent Data and Select Latches
Buffered Inputs
Three-State Complementary Outputs
Bus Line Driving Capability
Typical Propagation Delay: V_CC = 5V, C_L = 15pF, T_A = 25°C
- Data to Output = 18ns
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Technology family	HC
Function	Digital Multiplexer
Configuration	8
Number of channels	1
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)

228.702 mm² 24.33 x 9.4

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CD74HC354

具有三态输出的高速 CMOS 逻辑 8 输入多路复用器/寄存器

4000-306-326