These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 8 |
| IOL (max) (mA) | 6 |
| IOH (max) (mA) | -6 |
| Input type | TTL |
| Output type | CMOS |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Technology family | HCT |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| PDIP (N) | 20 | 228.702 mm² 24.33 x 9.4 |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
| TSSOP (PW) | 20 | 41.6 mm² 6.5 x 6.4 |
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