This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
| Number of channels | 4 |
| Technology family | ACT |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | TTL-Compatible CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 114 |
| IOL (max) (mA) | 24 |
| IOH (max) (mA) | -24 |
| Supply current (max) (µA) | 80 |
| Features | Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
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