These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
| Number of channels | 2 |
| Technology family | AS |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Bipolar |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 100 |
| IOL (max) (mA) | 20 |
| IOH (max) (mA) | -2 |
| Supply current (max) (µA) | 16000 |
| Features | Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | 0 to 70 |
| Rating | Catalog |
| PDIP (N) | 14 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SOP (NS) | 14 | 79.56 mm² 10.2 x 7.8 |
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