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TI(德州仪器) CY74FCT2543T
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  • TI(德州仪器) CY74FCT2543T
  • TI(德州仪器) CY74FCT2543T
  • TI(德州仪器) CY74FCT2543T
  • TI(德州仪器) CY74FCT2543T
  • TI(德州仪器) CY74FCT2543T
  • TI(德州仪器) CY74FCT2543T
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CY74FCT2543T

CY74FCT2543T

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具有三态输出和串联阻尼电阻的八路寄存收发器

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  • 封装 | 引脚 | 尺寸

The CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) inputs permit each latch set to have independent control of inputting and outputting in either direction of data flow. For example, for data flow from A to B, the A-to-B enable (CEAB) input must be low to enter data from A or to take data from B, as indicated in the function table. With CEAB low, a low signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the 3-state B output buffers are active and reflect data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2543T can replace the CY74FCT543T to reduce noise in an existing design.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

  • Function and Pinout Compatible With FCT and F Logic
  • 25-Output Series Resistors to Reduce Transmission-Line Reflection Noise
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 12-mA Output Sink Current
    15-mA Output Source Current
  • Separation Controls for Data Flow in Each Direction
  • Back-to-Back Latches for Storage
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 3-State Outputs

Supply voltage (min) (V)4.75
Supply voltage (max) (V)5.25
Number of channels8
IOL (max) (mA)12
IOH (max) (mA)-15
Input typeTTL
Output typeTTL
FeaturesDamping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Technology familyFCT
RatingCatalog
Operating temperature range (°C)-40 to 85
SOIC (DW)24159.65 mm² 15.5 x 10.3
SSOP (DBQ)2451.9 mm² 8.65 x 6
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