This octal registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC543A contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA, LEBA, and OEBA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 8 |
| IOL (max) (mA) | 24 |
| IOH (max) (mA) | -24 |
| Input type | TTL/CMOS |
| Output type | LVTTL |
| Features | Balanced outputs |
| Technology family | LVC |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (DW) | 24 | 159.65 mm² 15.5 x 10.3 |
| SSOP (DB) | 24 | 63.96 mm² 8.2 x 7.8 |
| TSSOP (PW) | 24 | 49.92 mm² 7.8 x 6.4 |