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TI(德州仪器) SN74AC563
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  • TI(德州仪器) SN74AC563
  • TI(德州仪器) SN74AC563
  • TI(德州仪器) SN74AC563
  • TI(德州仪器) SN74AC563
  • TI(德州仪器) SN74AC563
  • TI(德州仪器) SN74AC563
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SN74AC563

SN74AC563

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具有三态输出的八路 D 类透明锁存器

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The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE) does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 9 ns at 5 V
  • 3-State Inverting Outputs Drive Bus Lines Directly
  • Full Parallel Access for Loading
  • Flow-Through Architecture to Optimize PCB Layout

Number of channels8
Technology familyAC
Supply voltage (min) (V)2
Supply voltage (max) (V)6
Input typeStandard CMOS
Output type3-State
Clock frequency (max) (MHz)100
IOL (max) (mA)24
IOH (max) (mA)-24
Supply current (max) (µA)80
FeaturesBalanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode
Operating temperature range (°C)-40 to 85
RatingCatalog
PDIP (N)20228.702 mm² 24.33 x 9.4
SOIC (DW)20131.84 mm² 12.8 x 10.3
SSOP (DB)2056.16 mm² 7.2 x 7.8
TSSOP (PW)2041.6 mm² 6.5 x 6.4
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