This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (
) or clear (
) input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from -40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
| Number of channels | 2 |
| Technology family | AC |
| Supply voltage (min) (V) | 3 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 125 |
| IOL (max) (mA) | 24 |
| IOH (max) (mA) | -24 |
| Supply current (max) (µA) | 40 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |
| PDIP (N) | 14 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
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