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TI(德州仪器) SN74AS109A
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  • TI(德州仪器) SN74AS109A
  • TI(德州仪器) SN74AS109A
  • TI(德州仪器) SN74AS109A
  • TI(德州仪器) SN74AS109A
  • TI(德州仪器) SN74AS109A
  • TI(德州仪器) SN74AS109A
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SN74AS109A

SN74AS109A

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具有清零和预设功能的双通道 J-K 上升沿触发器

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These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

 

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

Number of channels2
Technology familyAS
Supply voltage (min) (V)4.5
Supply voltage (max) (V)5.5
Input typeBipolar
Output typePush-Pull
Clock frequency (MHz)105
Supply current (max) (µA)17000
IOL (max) (mA)8
IOH (max) (mA)-0.4
FeaturesClear, High speed (tpd 10-50ns), Positive edge triggered, Preset
Operating temperature range (°C)0 to 70
RatingCatalog
PDIP (N)16181.42 mm² 19.3 x 9.4
SOIC (D)1659.4 mm² 9.9 x 6
SOP (NS)1679.56 mm² 10.2 x 7.8
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