This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Widebus is a trademark of Texas Instruments.
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 18 |
| IOL (max) (mA) | 24 |
| IOH (max) (mA) | -32 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) |
| Technology family | ALVC |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SSOP (DL) | 56 | 190.647 mm² 18.42 x 10.35 |
| TSSOP (DGG) | 56 | 113.4 mm² 14 x 8.1 |
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