These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
| Number of channels | 6 |
| Technology family | AS |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Bipolar |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 100 |
| IOL (max) (mA) | 20 |
| IOH (max) (mA) | -2 |
| Supply current (max) (µA) | 45000 |
| Features | Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | 0 to 70 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| SOP (NS) | 16 | 79.56 mm² 10.2 x 7.8 |
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