This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-
series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.
NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.
Widebus, EPIC are trademarks of Texas Instruments.
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 16 |
| IOL (max) (mA) | 12 |
| IOH (max) (mA) | -32 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) |
| Technology family | ALVC |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SSOP (DL) | 48 | 164.358 mm² 15.88 x 10.35 |
| TSSOP (DGG) | 48 | 101.25 mm² 12.5 x 8.1 |
| TVSOP (DGV) | 48 | 62.08 mm² 9.7 x 6.4 |
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