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量产
特性
- 信噪比(SNR)：71.8 dBc（72.8 dBFS，至70 MHz、125 MSPS）
- 无杂散动态范围(SFDR)：85 dBc (至70 MHz、125 MSPS)
- 低功耗：750 mW (125 MSPS)
- 信噪比(SNR)：71.6 dBc（72.6 dBFS，至70 MHz、150 MSPS）
- 无杂散动态范围(SFDR)：84 dBc (至70 MHz、150 MSPS)
- 低功耗：820 mW (150 MSPS)
- 1.8 V模拟电源供电
- 1.8 V至3.3V CMOS输出电源或1.8 V LVDS输出电源
- 1至8整数输入时钟除法器
- 中频采样频率达450 MHz
- ADC内部基准电压源
- 集成ADC采样保持输入
- 灵活的模拟输入范围：1 V p-p至2 V p-p
- 欲了解更多特性，请参考数据手册
产品详情和应用
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.
In addition, the programmable threshold detector allows moni-toring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.
The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.
The AD9640 is availab
