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特性
- Four differential transmitters (Tx)
- Four differential receivers (Rx)
- Two differential observation receivers (ORx)
- Tunable range: 600 MHz to 6000 MHz
- Single-band and multiband (N x 2T2R/4T4R) capability
- Four individual band profiles within tunable range (band profiles define bandwidth and aggregate sampling rate of a channel)
- ADRV9044BBPZ-WB supports DPD for 400 MHz iBW/OBW
- Simplifying system thermal solution
- Power consumption-optimized DFE engines
- 125°C maximum junction temperature for intermittent operation, 110°C for continuous (operating lifetime impact at >110°C can be offset by operation at <110°C based on acceleration factors)
- Fully integrated DFE (DPD, CDUC, CDDC, and CFR) engine that reduces FPGAs resources and halves SERDES lane rate
- DPD adaptation engine for power amplifier linearization
- CDUC/CDDC—maximum eight component carriers (CCs) per each transmitter/receiver channel
- Multistage CFR engine
- Supports DTx (micro sleep) power saving mode in downlink
- Supports JESD204B and JESD204C digital interface
- Multichip phase synchronization for all local oscillator (LO) and baseband clocks
- Dual fully integrated fractional-N RF synthesizers
- Fully integrated clock synthesizer
产品详情和应用
The ADRV9044 is a highly integrated, system on chip (SoC) RF agile transceiver with integrated digital front end (DFE). The SoC contains four transmitters, two observation receivers to monitor transmitter channels, four receivers, integrated LO and clock synthesizers, and digital signal processing functions. The SoC meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell base-station radios, macro 3G/4G/5G systems, and massive MIMO base stations.
The receiver and transmitter signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for contiguous and non-contiguous multi-carrier base-station applications. The ZIF architecture has the benefits of low power plus RF frequency and bandwidth agility. The lack of aliases and out-of-band images eliminate anti-aliasing and image filters. This reduces both system size and cost, also making band independent solutions possible.
The device also includes two wide-bandwidth observation path receiver subsystems to monitor transmitter outputs. This SoC subsystem includes automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering. GPIOs that provide an array of digital control options are also integrated.
Multi-band capability is enabled by additional LO dividers and wideband operation. This allows two individuals band profiles within the tunable range, so maximizing use case flexibility.
The SoC has fully integrated DFE functionality, which includes carrier digital up/down conversion (CDUC and CDDC), crest factor reduction (CFR), digital predistortion (DPD), closed-loop gain control (CLGC) and voltage standing wave ratio (VSWR) monitor.
The CDUC feature of the ADRV9044 filters and places individual component carriers within the band of interest. The CDDC feature, with its e
