TI德州仪器_LTC4303_产品介绍

TI德州仪器 LTC4303 产品介绍

2026-04-14 0次

说明

Automatic Disconnect of SDA/SCL Lines when Bus is Stuck Low for ≥ 30ms
Recovers Stuck Busses with Automatic Clocking*
Bidirectional Buffer* for SDA and SCL Lines Increases Fanout
Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane
Pin Compatible with LTC4300A-1
±15kV Human Body Model ESD Protection
Isolates Input SDA and SCL Lines from Output
Compatible with I²C^TM, I²C Fast-Mode and SMBus Standards (Up to 400kHz Operation)
READY Open Drain Output
1V Precharge on All SDA and SCL Lines
High Impedance SDA, SCL Pins for V_CC = 0V
ENABLE Gates Connection from Input to Output
MSOP 8-Pin and DFN (3mm × 3mm) Packages

特性

The LTC^{^®}4303 hot swappable 2-wire Bus Buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. When a connection is made, the LTC4303 provides bidirectional buffering, keeping the backplane and card capacitances isolated. If SDAOUT or SCLOUT is low for ≥ 30ms (typ), the LTC4303 automatically breaks the data and clock bus connection. At this time the LTC4303 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will be enabled automatically when the bus becomes free.

Rise-time accelerator circuitry allows the use of larger pull-up resistors while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven high, ENABLE allows the LTC4303 to connect after a stop bit or bus idle occurs. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open drain output that indicates when the backplane and card sides are connected together.

*Patent Pending

应用