TI德州仪器_LTC4304_产品介绍

TI德州仪器 LTC4304 产品介绍

2026-04-14 0次

说明

Automatic Disconnect of SDA/SCL Lines when Bus is Stuck Low for ≥30ms
Fault Flag for Stuck Bus
Recovers Stuck Busses with Automatic Clocking*
Bidirectional Buffer* for SDA and SCL Lines Increases Fanout
Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane
Allows Bus Pullup Voltages Above and Below V_CC
±15kV Human Body Model ESD Protection
Isolates Input SDA and SCL Lines from Output
Compatible with I²C^TM, I2C Fast-Mode and SMBus Standards (Up to 400kHz Operation)
READY Open Drain Output
1V Precharge on All SDA and SCL Lines
High Impedance SDA, SCL Pins for V_CC = 0V
ENABLE Gates Connection from Input to Output
MSOP 10-Pin and DFN (3mm × 3mm) Packages

特性

The LTC^{^®}4304 hot swappable 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. When a connection is made, the LTC4304 provides bidirectional buffering, keeping the backplane and card capacitances isolated. If SDAOUT or SCLOUT is low for ≥30ms (typ), the LTC4304 automatically breaks the data and clock bus connection and FAULT will pull low. At this time the LTC4304 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will be enabled automatically when the bus becomes free. A logic low on the ACC input enables the LTC4304's rise-time accelerators. A logic high on ACC disables the rise-time accelerators, which allows SDA and SCL bus pull-up voltages below V_CC.

During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven high, ENABLE allows the LTC4304 to connect after a stop bit or bus idle occurs. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open drain output that indicates when the backplane and card sides are connected together.

*Patent Pending

应用